This application claims the benefit of Korean Patent Application No. 2001-000944, filed on Jan. 8, 2001, which is incorporated by reference herein in its entirety.
The present invention generally relates to memory devices and, more particularly, to ferroelectric memory devices.
Ferroelectric random access memory (FRAM) devices typically include a storage capacitor with a dielectric including ferroelectric material, such as a compound of lead zirconate and titanate. Cell architectures used for FRAMs include those using one transistor and one capacitor (referred to as a xe2x80x9c1TCxe2x80x9d cell configuration) and those using two transistors and two capacitors (referred to as a xe2x80x9c2TCxe2x80x9d cell configuration). A 2TC architecture is described in U. S. Pat. No. 4,873,664. A 1TC architecture is described in U. S. Pat. No. 5,978, 251. FRAMs, like DRAMs, may be classified as having a shared (or open) bit line structure, as described, for example, in U. S. Pat. No. 6,137,711, or a folded bit line structure, as described, for example, in U. S. Pat. Nos. 6,151,243, and 5,880,989. In general, data is read out of a FRAM by determining a charge on the capacitor by applying a predetermined voltage pulse signal to an electrode of the capacitor.
For the purpose of manufacturing a high-integrated FRAM, it is generally desirable to connect as many capacitors to a plate line as possible. However, the number of capacitors that can be connected to a plate line is generally limited by the capacitance of the capacitors. Because the number of memory cells that can be connected to a single plate line is typically small, it is often necessary to employ a relatively large number of circuits to control the plate lines. As a result, chip size may be increased.
FIGS. 1 and 2 illustrate conventional memory cell arrangements for 1TC memory cells, for shared and folded bit line architectures, respectively. In the shared bit line architecture shown in FIG. 1, memory cell array units MC10 are arranged in a matrix. A memory cell in the array unit MC10 includes an N-channel metal oxide transistor (NMOS) NO having a gate connected to an ith word line WLi and a channel connected between an ith bit line BLi and a capacitor CF0. Memory cells connected to the same bit line are connected to respective different plate lines PLi, PLi+1.
In the folded bit line architecture shown in FIG. 2, a two memory cell array unit MC20 is operated by adjacent bit lines BLi, BLi+1, and capacitors of the two memory cells of the array unit MC20 are respectively connected to the word lines WLi and WLi+1 and commonly connected to one plate line PLi. Such an arrangement can be more highly integrated than the open bit line architecture of FIG. 1. However, the number of the capacitors that can be connected to a single plate line is typically limited. Consequently, many circuits may be required to select the plate lines, which can increase chip size.
According to embodiments of the present invention, a ferroelectric memory device comprises a plurality of parallel word lines extending along a first direction, a plurality of parallel bit lines extending along a second direction transverse to the first direction, and a plurality of parallel plate lines extending along the first direction. A plurality of memory cells is arranged in rows and columns along the respective first and second directions, each of the memory cells including a transistor coupled to one of the word lines and to one of the bit lines and a ferroelectric capacitor connected to the transistor and to one of the plate lines such that the cells in respective rows are connected to respective word lines and the ferroelectric capacitors of first and second subsets of a row of memory cells are connected to respective first and second plate lines.
In some embodiments of the present invention, the plate lines are arranged as a plurality of pairs of adjacent plate lines such that a first pair of adjacent plate lines is separated from a second pair of adjacent plate lines by a pair of rows of memory cells. The memory cells in of a row of memory cells adjacent the first pair of adjacent plate lines may be connected to alternating ones of the first and second plate lines along the first direction. Respective columns of memory cells may be connected to respective bit lines or, alternatively, memory cells in a column of memory cells may be alternately connected to first and second bit lines along the second direction.
In further embodiments of the present invention, first and second pairs of adjacent plate lines are connected to memory cells in both rows of a pair of rows of memory cells that separate first and second pairs of adjacent plate lines. Respective columns of memory cells may be connected to respective bit lines or, alternatively, memory cells in a column of memory cells may be alternately connected to first and second bit lines along the second direction. In still other embodiments, a pair of adjacent bit lines are connected only to memory cells in first and second rows of memory cells disposed on opposite sides of the pair of bit lines.
In other embodiments of the present invention, plate lines are separated from one another by pairs of adjacent rows of memory cells. In some embodiments, a plate line may be connected only to memory cells in every other column along the first direction. Respective columns of memory cells may be connected to respective bit lines or, alternatively, memory cells in a column of memory cells may be alternately connected to first and second bit lines along the second direction.